1. Technical Field
The present invention relates to a semiconductor memory device.
2. Related Art
FIG. 7 is a plan view showing a conventional DRAM. FIG. 8 is a sectional view taken along the line VIII-VIII in FIG. 7. A DRAM 100 has bit lines 101, word lines 102, bit contacts 103, capacitor contacts 104 and capacitors 106. Each bit contact 103 connects the bit line 101 and a semiconductor substrate 105.
Each capacitor contact 104 connects the capacitor 106 and the semiconductor substrate 105. In the DRAM 100, two every adjacent bit lines 101 are aligned in parallel while keeping a constant pitch d1 (center-to-center distance).
A preceding technical literature relevant to the present invention may be exemplified by Japanese Laid-Open Patent Publication No. H6-5811.
The present inventors have recognized as follows. In the DRAM 100, the pitch d1 is set as large enough as ensuring a necessary level of margin for alignment between the bit lines 101 and the capacitor contacts 104. More specifically, the pitch d1 is set large enough so as to avoid undesirable contact between the bit lines 101 and capacitor contacts 104, taking process error in the manufacturing into consideration. As a consequence, portions provided with the bit contacts 103 have an unnecessarily large space between the bit lines 101. This may result in lowering in density of arrangement of the bit lines 101, and increase in the chip size.